The present invention relates to a dynamic type semiconductor storage device (DRAM) and a pseudo static type semiconductor storage device (pseudo SRAM) each of which has memory cells each comprised of a transistor and a capacitor and which have a self-refresh function. In particular, the present invention relates to a semiconductor storage device provided with a refresh timer circuit for generating a clock signal in a refresh cycle corresponding to leak characteristics of the memory cell capacitors in a self-refresh mode.
Generally, in the DRAM and the pseudo SRAM each having a built-in refresh timer circuit, the refresh cycle in the self-refresh mode is set to a fixed time interval based on the leak characteristics of preparatorily evaluated memory cells. More specifically, the refresh cycle is set in anticipation of the worst conditions attributed to the temperature dependency of a leak current after the completion of a chip and a fluctuation in the fabricating process. As a result, the refresh cycle hitherto used is shorter than the actually required refresh interval. That is, hitherto the refresh operation has been performed more frequently than required. This disadvantageously prevents a consumption current in the self-refresh stage from being saved.
With respect to the temperature dependency of the leak current, the leak current is reduced by about half every time the temperature falls by 10.degree. C. Therefore, it should be acceptable to prolong the refresh cycle (time interval of the refresh operation) to about the double every time the temperature falls by 10.degree. C. On the other hand, with respect to the consumption current in the self-refresh mode, it is approximately in inverse proportion to the refresh cycle. Therefore, if a refresh time interval can be set in accordance with the actual leak current, then it will be able to reduce the consumption current in the self-refresh mode especially when the temperature is low.
In view of the above, Japanese Patent Laid-Open Publication No. HEI 2-137186, Japanese Patent Laid-Open Publication No. SHO 61-50287, Japanese Patent Laid-Open Publication No. SHO 61-139995, Japanese Patent Laid-Open Publication No. SHO 61-214297 and Japanese Patent Laid-Open Publication No. SHO 62-40694 propose semiconductor storage devices whose refresh cycle is set according to the temperature dependency of the leak current as described below.
(First Prior Art)
In a semiconductor dynamic memory device disclosed in the Japanese Patent Laid-Open Publication No. HEI 2-137186, the leak current of a pn junction element having a temperature-leak characteristic similar to that of a memory cell is monitored instead of monitoring the leak current of the memory cell.
FIG. 9 shows a timing generator for generating a self-refresh clock of this semiconductor dynamic memory device. In FIG. 9 are shown a pn junction 511 provided on a semiconductor substrate, a p-channel MOS transistor 512, a voltage detector 513 in which an even number of CMOS inverters are connected in series, and a delay circuit 514 for delaying the output waveform of the voltage detector 513, those totally constituting a first oscillator 518. There are further shown a second oscillator 519 which can be started and stopped by a signal, and a counter circuit 520. Each of the delay circuit 514, the second oscillator 519 and the counter circuit 520 is formed by a CMOS. The source of the transistor 512 is connected to a power source 517 and its drain is connected to a first terminal (the n-type semiconductor side) 515 of the pn junction 511. A second terminal (the p-type semiconductor side) 516 of the pn junction 511 is connected to the semiconductor substrate or the ground potential The first terminal 515 is connected to the input of the voltage detector 513, and the output of the voltage detector 513 is connected to the gate of the transistor 512 via the delay circuit 514. The output of the voltage detector 513 is also connected to a start signal input terminal 521 of the second oscillator 519, while the output of the second oscillator 519 is connected to the counter circuit 520 and at the same time drawn out as a self-refresh clock to an output terminal 523. The output of the counter circuit 520 is connected to a stop signal input terminal 522 of the second oscillator 519.
The pn junction 511 shown in FIG. 9 and pn junctions included in memory cells are fabricated on an identical substrate through an identical fabricating process.
The operation of the semiconductor dynamic memory device of the first prior art will be described below. FIG. 10 is a timing chart for explaining the operation of the first oscillator 518 shown in FIG. 9, and FIG. 11 shows an enlarged view of a portion XI enclosed by the dashed lines in FIG. 10. If the first terminal 515 is charged up to a power voltage of 5 V and thereafter disconnected from the power source, then the voltage at the first terminal 515 reduces as the time elapses due to a leak current in the reverse direction of the pn junction 511. When this voltage reaches a detection level to be detected by the voltage detector 513, the output waveform of the voltage detector 513 is inverted to a low-level. In response to this, after a lapse of a delay time D, the delay circuit 514 also becomes inverted so as to apply a low-level voltage to the gate of the transistor 512. Then, the p-channel transistor 512 is turned on to make the power source 517 continuous with the first terminal 515. Then, the voltage at the first terminal 515 starts to increase due to a current flowing from the power source 517, and the output of the voltage detector 513 switches to a high-level when the voltage at the first terminal 515 again reaches the voltage detection level. Subsequently, after a lapse of the delay time D a high-level voltage is again applied to the gate of the transistor 512 to turn off the transistor 512, so that the first terminal 515 is disconnected from the power source. The first terminal 515 is completely charged up to the power voltage during the delay time D, and when it is disconnected from the power source, the voltage restarts to reduce due to the leak current of the pn junction 511. The above operations are repeated to continue an oscillating operation. This oscillation cycle is roughly determined by the time of the voltage at the first terminal 515 reducing from the power voltage to the voltage detection level. Therefore, the cycle becomes shorter at a high temperature at which the reverse leak current of the pn junction 511 increases, and becomes long at a low temperature at which the leak current reduces.
(Second Prior Art)
Japanese Patent Laid-open Publication No. SHO 61-50287, Japanese Patent Laid-Open Publication No. SHO 61-139995, Japanese Patent Laid-Open Publication No. SHO 61-214297 and Japanese Patent Laid-Open Publication No. SHO 62-40694 teach to use transistors and capacitors of memory cells to monitor the leak current of the memory cells. As a representative example, the construction disclosed in the Japanese Patent Laid-Open Publication No. SHO 61-50287 will be described with reference to FIG. 12 and FIGS. 13A, 13B, 13C and 13D.
In a dynamic memory including an automatic refresh control circuit shown in FIG. 12, memory cells are each constituted of one storage retaining capacitor and one transfer gate which are connected in series with each other. A leak monitor circuit 610 has the same construction as that of the memory cell, and one transfer gate Q and one capacitor C are connected in series with each other between a power source V.sub.DD and a specified potential terminal (ground terminal). A CMOS inverter 611 connected with the leak monitor circuit 610 is supplied with a voltage retained in the capacitor C. In the CMOS inverter 611, a p-channel MOS transistor Q.sub.P is formed to have a greater transconductance than that of an n-channel MOS transistor Q.sub.N. With this arrangement, a threshold voltage V.sub.TH is set to be higher than 1/2 V.sub.DD (V.sub.DD is the operating power voltage) by a specified value. A first control circuit 613 shapes the waveform of output of the CMOS inverter 611. A self-excited type oscillator 614 enters into an oscillation mode upon receiving the output of the first control circuit 613 to execute an oscillating operation. A refresh address counter 615 resets itself upon receiving the output of the first control circuit 613 and forms a refresh address through counting of outputs from the oscillator 614. This address counter 615 sends a refresh address to a row decoder for selectively driving a word line of the memory cell array. A second control circuit 616 generates a pulse of a constant width upon receiving an overflow output from the refresh address counter 615 to turn on the transfer gate Q of the leak monitor circuit 610 by means of this pulse to thereby charge the capacitor C.
Next, the operation of the automatic refresh control circuit will be described with reference to FIGS. 13A through 13D. First, the transfer gate Q of the leak monitor circuit 610 keeps its on state from a time t.sub.1 to a time t.sub.2 by an output P.sub.2 of the second control circuit 616, whereby the capacitor C is charged and a value of 1 is written into a storage node N between the transfer gate Q and the capacitor C. The potential of this node N can be regarded as a representative leak state of the memory cells. That is, when the leak current of the memory cells is large, the potential of the node N speedily becomes zero volts. When the leak current is smaller, it takes a longer time for the potential at the node N to reach the zero volts. At a time point t.sub.3 when the potential at the node N becomes below the threshold voltage V.sub.TH of the CMOS inverter 611, the inverter output potential changes from the 0-level to the 1-level, and this output is subjected to waveform shaping in the first control circuit 613. Output of the first control circuit 613 resets the refresh address counter 615 and brings the oscillator 614 into the oscillation mode. As a result, the output of the oscillator 614 oscillates, and the counter 615 counts oscillations to form a refresh address. When the counter 615 makes a round of counting operation and an overflow occurs in the counter at a time t.sub.4, the overflow output signal is supplied to the second control circuit 616, and the leak monitor circuit 610 is driven again by the pulse generated in the second control circuit 616, thereby recharging the capacitor C.
According to the first prior art shown in FIG. 9, the leak current of the pn junction having a temperature-leak characteristic similar to that of memory cells is monitored in order to monitor the leak current of the memory cells. However, since the leak current of the pn junction is normally very small, a very large pn junction region has been required so as to obtain a leak current sufficient to be monitored. This has consequently led to the disadvantage that the chip size increases by the increased area of the pn junction region.
On the other hand, the second prior art utilizes the memory cell transistors and capacitors to monitor the leak current of the memory cells. However, the leak of the capacitors normally occurs due to the defect of the pn junction portion or the insulating film. Therefor, the leak current differs significantly among the capacitors. This disadvantageously makes it difficult to adjust the refresh cycle to an appropriate value. Furthermore, since the leak current of a capacitor is normally very small, in order to monitor the leak current well, it is required that each capacitor has a very large size such that a sufficient leak current is generated. The requirement disadvantageously invites the increase of the chip size.